Please find below a link to PDFs of the JUG 2020 customer presentations.
|Intel||Evgeny Wiener||Scaling up Formal Verification with FV Engines Jobs in External Cloud|
|Arm||Nicolas Phan||Arm Project Zero – Zero Security Flaws with Formal Methods|
|Silicon Labs||Chester Yu||Design Bring-up without a Testbench: Leveraging TCL for Automated Checks|
|TI||Noor Elahi||ORION – RegMap Verification Flow|
|Intel||Sumit Kumar Kulshreshtha||A Novel Approach for Verifying a CNN Based Image Processor|
|STMicro||David Vincenzoni||Formal Verification Signoff for Digital IP: Can We Use It?|
|Intel||Hao Chen||A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization|
|Arm||Kamayani Rai||Safe Clocking: A Formal Approach to CDC and RDC Verification|
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