With the increasing popularity of multi-chiplet designs that address Moore’s law slowdown and reticle size limitations, leading foundries are offering multiple advanced packaging and die stacking options for different applications. EDA companies have had to innovate to provide integrated and IC-centric tools while building accurate system-level models to find the fastest and most efficient path for 3D-IC design and analysis.

In this four-part CadenceTECHTALK series, learn how to properly plan and implement stacked digital SoCs, analog/mixed-signal designs, and entire 2.5-D/3-D systems, including meeting system-level power and thermal analysis requirements through an integrated 3D-IC solution.

CadenceTECHTALK: Efficient Multi-Chiplet Design with Integrity 3D-IC Unified Platform
February 23, 2022

Multi-chiplet design and packaging introduces extra design and analysis requirements like system planning, bump alignment, TSV and micro-bump insertion and extraction, electrothermal analysis, cross-die STA, and inter-die physical verification, which must be considered early during planning and implementation. The new Cadence® Integrity™ 3D-IC platform provides innovative technology that proactively looks ahead through integrated planning, implementation, and analysis to address the new requirements of 3D-IC design and signoff for different packaging styles.

In this session, learn about the different packaging styles, innovative multi-technology database, integrated system planner, and an embedded analysis flow manager inside the Integrity 3D-IC platform, which provide a comprehensive, yet modular multi-chiplet design solution to help shorten the design cycle for all aspects of 3D-IC design and signoff.


CadenceTECHTALK: System Planning and Implementation for Different 3D-IC Design Styles
March 9, 2022

System planning is a major part of multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving for different types of designs, a top-down and a bottom-up approach for implementation is possible.

In this session, learn about the different approaches to 3D partitioning, implementation, and unique capabilities available with Integrity 3D-IC platform for bump planning, interposer routing, and top-down 3D partitioning and implementation available with the Integrity 3D-IC platform.


CadenceTECHTALK: 3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hierarchical Analysis
March 23, 2022

A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis is extremely critical in 3D-ICs, since changing the die stack up later in the design process is incredibly challenging, or not possible.

In this session, get a chip-centric perspective on performing PI and thermal integrity analysis in 3D-ICs from early planning to signoff. 


CadenceTECHTALK: Overcoming System-Level 3D-IC Electrical and Thermal Challenges
April 6, 2022

Electronic products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise.

In this session, we will address these concerns through simulation during system planning and continuing through signoff to accelerate the 3D-IC design cycle and avoid expensive design re-spins. Therefore, it is important to have a vision of thermal gradients, signal quality, and power delivery across chiplets, packages, and PCBs to not only address any risks, but also optimize the design’s TSV locations for maximum performance.


For more information, please visit our 3D-IC Solution website »