Signal and Power Integrity in the Era of AI and Chiplets

Chiplet integration and synchronized AI workloads have taken away the slack that once let you treat signal and power integrity as separate, solvable problems. This paper shows why these effects now couple, and how to close them before tapeout.

What you'll take away

• See why chiplet integration ties crosstalk, reflection, loss, skew, and droop into one problem you can no longer budget separately
• Understand how synchronized AI switching makes NEXT, FEXT, and power-supply-induced jitter add up instead of averaging out
• Learn to resolve loss and reflection in layout geometry, and co-simulate SI and PI from the floorplan forward with Sigrity X