Overview
DesignCon 2025 education sessions are now available for download. Learn from Cadence experts and customers how to enhance your electromagnetic, electronic, and thermal designs. Click the links to access the presentations.A Study on the Thermal Implications of Flip-Chip Technology for mmWave MMIC Amplifiers
Flip-chip enables high-density packaging with a smaller form factor, improved interconnects, and enhanced signal integrity. This study compares thermal management in GaAs and GaN flip-chip MMICs with copper pillar bumps. Results confirm flip-chip's viability for high-power applications.
Platform PDN Optimization and Sign-off with IBIS-approved Streamlined Power Integrity Model (SPIM)
Learn how semiconductor and EDA companies are collaborating to advance power integrity analysis using SPIM keywords in IBIS models - from model components to EDA tool automation and signoff with trusted power integrity engines.
System-Level C-PHY High-Speed Signal Integrity Analysis for Mixed and Virtual Reality Systems
This study explores a simulation methodology for MIPI C-PHY in MR/VR systems, addressing signal integrity challenges in RFPCs. Partnering with Meta, we analyze high-speed routing across interconnects using Clarity 3D Solver and Optimality. We evaluate reference plane transitions, Pogo Pin interconnects, and virtual grounds, validating compliance with SystemSI through time-domain analysis.
Case Study: How to Sign Off Your UCIe Interface
This case study covers the development of a UCIe interface in a Cadence IP test package. Learn about UCIe specifications, design and analysis tool requirements, and integration of chiplets with UCIe PHYs into various packages, including organic and advanced silicon interposers. Finally, watch a live demo of Cadence tools creating an industry-compliant UCIe interface.
Accelerating Time-to-Market in the Chiplet Era
Discover how our advanced chiplet reference platform accelerates ADAS design. The industry faces two trends: centralized computing for software-defined vehicles and disaggregated chiplets for independent verification. Our multi-chipset architecture balances both, ensuring interoperability and security. Learn how we address SiP trustworthiness, functional safety (ISO 26262), and cybersecurity (ISO/SAE 21434).
The Role of EDA as Chips Transform Into 3D Systems
As the industry shifts from Moore’s Law to More-than-Moore, IC and system design convergence demands advanced EDA design flows. Seamless cross-domain co-design is key to achieving high performance at low cost. Chiplet-based architectures and SiP offer a flexible, cost-effective alternative to SoCs. This presentation explores the challenges of 3D heterogeneous design and how EDA solutions address them.
Accelerate Silicon Interposer Development with Integrated Design and Analysis
Signal and power integrity are crucial for silicon interposer development, but moving data between EDA tools can slow progress. This session explores how intelligent selective cutting within a single EDA tool flow accelerates development. Topics include AI-optimized constraints, 3D FEM modeling for chiplet interfaces, UCIe compliance signoff, and Power Integrity analysis for stable, efficient power delivery.
VIDEO: Cadence Measurement and Correlation at DesignCon 2025
Cadence’s Gary Lytle, Director of Product Management, explains how to use real-world measurement data as a foundation for validating electromagnetic (EM) simulations.